When a semiconductor device such as a metal-oxide-semiconductor field-effect transistors (MOSFETs) is scaled down through various technology nodes, high-k dielectric material and metal are adopted to form a gate stack. In addition, strained source/drain features have been implemented using epitaxial (epi) silicon germanium (SiGe) to enhance carrier mobility and improve device performance in p-type devices. Further, raised source/drain features have been implemented using epi silicon (Si) in n-type devices. However, current techniques to perform dual epi process for n-type and p-type devices have not been satisfactory in all respects. For example, voids may be formed between the gate structure and the strained source/drain features during processing which can degrade device performance.